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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
Zheng Wang
Hardcover. Springer 2017-06-08.
ISBN 9789811010729
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Publisher description
This book introduces a novel framework for accurately modeling the errors in nanoscale technology and developing a smooth tool flow at high-level design abstractions to estimate error effects, which aids the development of high-level fault-tolerant techniques. In total, the book presents 6 solutions for reliability estimation (3 for fault injection and 3 for analytical estimation) and 5 techniques for reliability exploration (3 for architectural level and 2 for system-level). It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Book reviews » High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Computer Architecture and Design Methodologies)
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